MicroPython Forum (Archive)

This is a bit complicated because of the variable-sized flash blocks. It will require some changes to stm32/flash.c and stm32/flashbdev.c yes, I got it already. I decided to expand FlashFS by 128Kb (sector 5) the scheme in "stm32f405.ld" is as follows: FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 102...

I don't see where you're defining _sstack, but what it looks like is happening is that you're now making the heap use the entire SRAM1+SRAM2 (after ebss), which means it will collide with the stack. I imagine this will look like it's working until it doesn't. 0x20020000 is the same as ORIGIN(RAM) +...

The heap is limited by the available RAM. The default configuration uses all available RAM (left over after .bss and .data). The only exception is that the CCM is reserved for the block cache. Making that available to the heap would require supporting multiple non-contiguous regions, but isn't curr...

STM32F405. Flash 1024K, max Flash page size 128K, SRAM1 128K, CCM 64K (non contiguous, CPU only) I plan to submit a PR for just the L475 and F405 for code review first, then update the whole STM32 family to make it easier to adjust memory allocation. There are basically four changes: Hello! I'm try...