MicroPython Forum (Archive)

It should be mentioned that PYBLITE doesn't use a crystal for the RTC but an RC oscillator. However, it is pretty easy to solder in a TH crystal.

MPY epoch is 2000-01-01 instead of unix epoch, which is 1970-01-01. Note:
I'm not sure if time.UNIX_TIME is defined in the master repository. It is just a constant

If I remember correctly the (usually unwanted) parasitic capacity from overlapping gate and drain is indeed called Miller capacity.

BTW, it is interesting that Rds seems to be constant. So I guess it is just a variation of the gate area or using multiple gates.

Just a quick test run. Scope probe connected with two wet shoelaces to Y5 and GND of a PYBLITE to simulate lousy wiring.
The 150Ohm load was just measured with a step whereas other tests used a pulse.
GPIO_SLOW_150OHM
GPIO_SLOW_OPEN
GPIO_FAST_OPEN

If your intention is to use a pin as combined input/output you may have to change your logic. If it is just an output, use it in OUT_OD mode.

Let's assume the relay works fine if Vin is at +5VDC and IN is either connected to Vin or GND. Repeat the test with Vin at 4V. If this also works fine I would recommend to use the output in open-drain mode with an external pull-up resistor connected to Vin. Note: If it is just a plain relay without ...

The key phrase is "(with a relaxed V OL/V OH)". In fact at least on STM32 devices we tested the speed of a GPIO output affects Rds. Which means you can source 20 mA but the voltage drops more or less depending on the output speed.

Usually variable output speeds are implemented with several FETs of different size which results in different Rdson and gate capacity.
This allows different driver strengths and in consequence different output speeds. A typical application is to reduce EMI by avoiding excessive slope rates.

jpegtran has to be run on a host computer. Try this one.