MicroPython Forum (Archive)

Hi pythoncoder,

One more test:
whatever the order I start the write_timed's in, DAC 1 before DAC 2 or the reverse,
it's always the DAC 2 pin X6 signal that is inverted.

At least there is no random behavior, and we can consider that as a "not yet documented feature", not a bug.

Thanks a lot for your answer. With a rather slow signal, I thought to control the phase. Please find here the details: The buffer is a 40 bytes bytearray with a timer Timer(6, freq=2400, prescaler=0, period=34999, mode=UP, div=1) sf=84000000 it gives a pretty slow 60 Hz signal. I can even introduce ...

On the pyboard the 2 DACs give opposite polarities when used together. (MicroPython v1.9.3 on 2017-11-01; PYBv1.1 with STM32F405RG) i.e: issuing dac1.write_timed(buf1, timer6, mode=DAC.CIRCULAR) dac2.write_timed(buf2, timer7, mode=DAC.CIRCULAR) with the same data in both buffers, the 2 outputs have ...