micropython frequency measuring

[pythoncoder]

10MHz is seriously pushing it even using assembler. I'd use an external chip to implement a frequency divider to reduce the frequency presented to the Pyboard.

[ebike]

cross-posted .... thanks for the reply ..

I can't divide down as the PLL has to respond to frequency and phase of both reference and input signals

[dhylands]

To measure a 10 MHz frequency assumes that the signal will be high for 50 nanosecs and low for 50 nanosecs. 50 nanoseconds is about 8 CPU instructions, assuming no wait states and single cycle instructions.

At 168 MHz, 1 CPU cycle is about 6 nanoseconds.

[ebike]

Guess I will have to look at another solution.
I can use a DDS chip from Analog devices for output ... but need to find something else for freq input ...

Cheers,

[pythoncoder]

It's hard to comment without a detailed understanding of your application but in general it is possible to implement PLL's where the input and reference frequencies are reduced by frequency dividers. I have also encountered PLL's where the frequency is reduced in the analog domain by means of a mixer and filter.

Another approach is to implement the phase comparator with discrete logic: if both signals have 1:1 mark space an exclusive OR gate can be used for the purpose. Filter its output, feed it into a Pyboard ADC, and use the Pyboard to control a VCO or digitally controlled oscillator. The Pyboard then only needs to support the loop bandwidth rather than the signal frequency.

[ebike]

Hi,

I was thinking along similar lines.

My thoughts where to input the frequency to a digital phase comparator (which is one line of Python code) the other input to the phase comparator is the reference frequency (output freq). The output of the phase comparator goes to a biquad digital filter (in Python), the output of that goes to a VCO, and I feel the best for that task is an external DDS as I need sinewave generation at up to 10Mhz.

The only real question is if we divide down both reference and input signals, is the phase difference preserved ...
(I need to keep a 90deg phase diff between input and reference signals)

[pythoncoder]

Alas phase difference is not preserved: the PLL will adjust for 90 degrees between its inputs. With a 2:1 divider the inputs would be 180 degrees out of phase (and so on for higher ratios).

[ebike]

Dang, suspected as much. Back to the drawing board.

EDIT: .. maybe a better platform would be measuring the input period directly with a RP3 in assembly .... (very off topic for this forum)

[jms]

You need to start with a specification like how often and how accurate.

The thing is a cheapo microcontroller can do this trivially as almost all of them have loads of timers and counters. Moving to a heavier platform like this makes things more difficult.

Jon

[dhylands]

I think that it may be possible to measure the frequency of a 10 MHz signal on the pyboard (at least to measure the high time of the signal.

Some of the channels also have an XOR mode which might be useful for doing the phase alignment as well, but I'm not 100% sure.

It would require using chained timers, which micropython doesn't directly support. The idea is that you setup one timer as say a rising edge input capture and use that to trigger another timer which does a falling edge input capture.

The count on the falling edge input capture will reprsent the high time of your clock pulse. Timers 1 & 8-11 can count as fast as 168 MHz, the remaining ones can count as fast as 84 MHz.

See page 552 of the RM0090 reference manual where it talks about trigger mode.
http://www.st.com/content/ccc/resource/ ... 031020.pdf

The closest example I have in MicroPython was an example of gated mode: https://github.com/dhylands/upy-example ... r/gated.py