Hello. I'd like to be able to run some C code on the second core of the ESP32.
It looks like the second core has been disabled in sdkconfig.h using the CONFIG_FREERTOS_UNICORE.
How can I re-enable this second core?
I've tried simply changing sdkconfig.h to:
#define CONFIG_FREERTOS_UNICORE 0
However, I get this error:
I (80) cpu_start: Pro cpu up.
I (80) cpu_start: Starting app cpu, entry point is 0x40081b14
0x40081b14: call_start_cpu1 at cpu_start.c:?
I (0) cpu_start: App cpu up.
I (83) heap_init: Initializing. RAM available for dynamic allocation:
I (89) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (95) heap_init: At 3FFB27D8 len 0002D828 (182 KiB): DRAM
I (101) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (108) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (114) heap_init: At 4008A684 len 0001597C (86 KiB): IRAM
I (120) cpu_start: Pro cpu start user code
I (139) cpu_start: Starting scheduler on PRO CPU.
Guru Meditation Error: Core 1 panic'ed (LoadProhibited)
. Exception was unhandled.
Core 1 register dump:
PC : 0x4008786f PS : 0x00060033 A0 : 0x800d2071 A1 : 0x3ffe7ce0
0x4008786f: vTaskEnterCritical at ??:?
A2 : 0x00000001 A3 : 0x3ffb1e60 A4 : 0x00000001 A5 : 0x00000000
A6 : 0xffffffff A7 : 0x3ffe7ce0 A8 : 0x8008785c A9 : 0x3ffe7cb0
A10 : 0x00000001 A11 : 0x3ffe7d14 A12 : 0xb33fffff A13 : 0x00000000
A14 : 0x00000000 A15 : 0x3ffe7cb0 SAR : 0x00000000 EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000051 LBEG : 0x4000c2e0 LEND : 0x4000c2f6 LCOUNT : 0x00000000
Core 1 was running in ISR context:
EPC1 : 0x4008786f EPC2 : 0x00000000 EPC3 : 0x00000000 EPC4 : 0x00000000
0x4008786f: vTaskEnterCritical at ??:?
Backtrace: 0x4008786f:0x3ffe7ce0 0x400d206e:0x3ffe7d50 0x40081b82:0x3ffe7d80 0x40081b63:0x3ffe7da0 0x40007c31:0x3ffe7dc0 0x4000073d:0x3ffe7e30
0x4008786f: vTaskEnterCritical at ??:?
0x400d206e: esp_crosscore_int_init at ??:?
0x40081b82: start_cpu1 at ??:?
0x40081b63: call_start_cpu1 at cpu_start.c:?
Rebooting...
It looks like some of the Micropython forks have successfully enabled this second core. What's changes are required to make it work?
How to enable second core (CPU1 APP CPU) on ESP32?
Re: How to enable second core (CPU1 APP CPU) on ESP32?
The ESP32 uses RTOS to coordinate between the CPUs. One is for communications and the other for applications Loboris has a port for the ESP32 that recognizes this and enables both CPUs. It does a few other things too.
https://loboris.eu/forum/Thread-Info-Mi ... AM-support
https://loboris.eu/forum/Thread-Info-Mi ... AM-support