wdt reset on wake from deepsleep

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devnull
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wdt reset on wake from deepsleep

Post by devnull » Sun May 27, 2018 6:07 am

Have an intermittent problem with deeps sleep and are getting a WDT reset immediately after waking up from a 5 minute deep sleep.

There is a known problem with this happening in rev0, however it is supposed to be fixed by increasing the delay to 2 seconds which is what it defaults to:

sdconfig.h

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#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000

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ets Jun  8 2016 00:22:57

rst:0x5 (DEEPSLEEP_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
ets Jun  8 2016 00:22:57

rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
ets Jun  8 2016 00:22:57

rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0018,len:4
load:0x3fff001c,len:4484
load:0x40078000,len:0
load:0x40078000,len:11816
entry 0x4007a9fc
W (29) boot: PRO CPU has been reset by WDT.
W (29) boot: WDT reset info: PRO CPU PC=0x3396be19
W (29) boot: WDT reset info: APP CPU PC=0x96e02d61
I (221) cpu_start: Pro cpu up.
I (221) cpu_start: Single core mode
I (221) heap_init: Initializing. RAM available for dynamic allocation:
I (225) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM
I (231) heap_init: At 3FFC5098 len 0001AF68 (107 KiB): DRAM
I (237) heap_init: At 3FFE0440 len 00003BC0 (14 KiB): D/IRAM
I (243) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM
I (250) heap_init: At 4008DD1C len 000122E4 (72 KiB): IRAM
I (256) cpu_start: Pro cpu start user code
I (50) cpu_start: Starting scheduler on PRO CPU.
EDIT
===
I can confirm that this is rev0 silicon.

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CHIP_VERSION           Chip version                                      = 0 R/W (0x0)
CHIP_PACKAGE           Chip package identifier                           = 0 R/W (0x0)
Last edited by devnull on Sun May 27, 2018 6:40 am, edited 2 times in total.

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