Hi Bob, @roberthh and @pythoncoder give good advice about grounding and using a star ground. This is not always enough. It helps to understand all the ways noise can get into sensitive circuits. I do a lot of mixed signal design and I will explain how I analyse noise sources and optimise PCB layouts. I have looked at your PCB design and will refer to it below.
First think about noise sources. In your case the noise is most likely being generated by spikes and surges in the 3V3 demand by the MCU and peripherals. The accelerometer I2C interface will generate bursts of fast edge pulses at probably 400KHz. There will be harmonics well into the MHz depending on the slew rate ot the GPIO's. During ADC conversion the ADC unit will wake up and very quickly do 12 successive approximations generating demands on the power supply again in the MHz range. In both cases there is a peak demand for power. Some will come form the bypass caps, the rest through the V+ and GND traces from the power supply V+. There will be spikes on V+ and transient voltage drops in the GND plane between the pyboard and power supply capacitor C3.
How does this noise couple into the analog circuits? By coupling (radiated) or injected (conducted).
If an aggressor trace (noisy signal, eg SPI CLK) runs close to a receptor trace (analog line) the noise will couple capacitively. This can be reduced by reducing the mutual capacitance, increasing the aggressor impedance, reducing the receptor impedance or reducing the slew rate. When digital lines have to enter the analog world try to keep the traces separated and perpendicular. Add series resistors to the digital lines and decoupling capacitors to the analog input pins. For the SPI lines there is a limit as to how far you can filter them but lowering the SPI CLK frequency will help. The filter resistors or ferrite beads should be on the digital side and the shunt capacitors on the analog side so the control inputs to analog ICs are quiet with respect to their (analog) GND.
If noise current flows in a trace and back in a return trace, eg GND, the loop it flows around will couple that noise inductively into other traces. Minimise the area of current loops, eg the V+ and GND connection to the pyboard. This is done my making sure the trace and its return are close together, or the trace is over a GND plane. Note that at noise frequencies the return current only flows in the GND plane directly under the trace and not point to point. If you have a break in the plane the return current will flow around the gap and add area to the loop. So don't run noisy power traces over gaps in the GND plane, run them around the gap over the plane. The same applies on the analog side, keep the analog signal lines very close to their return GND lines. By reducing their loop area they won't receive as much noise.
Traces and even GND planes are inductive. Noise current flowing through GND traces or plane will generate significant voltage drops. If analog signal return or analog supply return shares this GND the noise will be coupled into the analog signal. This is where the star GND comes in. Keep all the noisy digital signal and power return in half the GND plane and keep the other side quiet. This will fail if there is noisy current flowing through the star. You have to filter all digital signal lines and the analog power to prevent this happening. When the digital circuit has a V+ current spike it will draw power from everywhere. Some will be from the power supply but some will be from the analog IC bypass caps which are connected to V+. The return path from the analog bypass caps will flow through the analog GND plane and through the star point. You have to add an LC or RC filter in series with V+ to generate a decoupled VA+. Likewise filtering the digital lines that control analog circuits will help.
With careful layout you don't need a star point. It is normally recommended to put a star point under an ADC, but you can't have a star point when there are multiple ADCs. So I draw a dividing line across the PCB which defines the analog / digital boundary. There is no cut in the GND plane. You just have to be very careful to ensure that there is no noisy current flowing across the line and no noisy current flowing parallel and close to the line which could induce voltage drops from one side of the analog half to the other.
There can also be external noise sources generating GND current. There is a loop through the Guitar amplifier mains GND, the Laptop mains, the USB cable and the audio cable. If your Laptop has a two pin mains plug then there will be about half supply voltage (60 to 120 VAC) on the USB cable at probably under 100uA. This is due to a 4n7 EMC cap between the mains rectifier and the DC output. This would flow down the USB cable and back up the audio cable to the amplifier.
Most of the digital noise will be RF. This gets into audio two ways. The power supply will droop when there is high frequency activity. The time constant of this droop depends on the capacitor size and may well be directly audible. RF is often rectified in the analog circuits, either in the substrate isolation diodes, input protection diodes or the input transistors or fets. If you have a burst of high frequency activity for 100 uSec the envelope is a pulse that looks like a half cycle at 10 kHz. The rectification works like a crystal set. It AM demodulates the RF burst and makes audible noise. It is very important to keep all noise pulses and GND bounce well below 600mV to avoid this. I have often seen more than 1V GND bounce on boards without a good GND plane.
If you are going to make another version of your board I would do the following:
1. Drop the V+ plane and route the V+ like the V-. It is better to use both sides to build a lower impedance GND plane that provides a return path close to every signal. Once you have a really low impedance GND plane use bypass caps to reduce the impedance of the supplies. Try to get the plane to pour between the DIP and connector pads if design rules permit. Using rounded rectangular pads (long and narrow) will help. Spread out vias so you don't create big holes in the plane.
2. Move as many traces to the top side as possible, with only short jumper traces on the bottom.
3. Pour as much GND on both sides as possible and stitch them together with lot of vias. Whenever you need to run a trace on the bottom side keep it short and jump back to top. When a trace changes layers add a GND via nearby to allow the return current to follow the signal without creating a loop to the nearest GND stitching via. Try to patch over holes in the bottom plane with the top plane. Ideally you won't be able to see through the board when you hold it up to the light.
4 Put a cut in the GND plane on both sides between the pyboard and the analog circuit. The star point should be at the power supply. This is ok since you are not using the STM32 ADC. If you use the ADC then the star should be at AVDD but you may have to use separately regulated analog supplies. You don't want the analog supply current going through AVDD to the power supply GND via the noisy pyboard GND pin.
5. Make the power supply low noise and low impedance. Use a good low ESR high frequency filter cap like Panasonic FC series and a 100nF ceramic in parallel.
6. Filter the analog V+ with an LC filter.
7. Don't cross the GND plane split with noisy lines, eg SPI. Run the SPI around the power supply, over the star point. Otherwise you create a big loop area between the SPI and the GND return which has to run through the star point. Add series resistors at the pyboard end and small bypass caps after you cross the star point. Steady state control lines, eg direct GPIO to analog switch control should be filtered because they will be modulated with digital GND or VCC noise. For static lines use at least 1k, 100nF. For clocked lines it depends on how low you can run the clock speed and whether the inputs can tolerate slow clocks (do they have schmitt trigger inputs?). In the STM32 use the lowest GPIO port speed that works.
8. Try to keep the SPI lines separated and orthogonal to the analog lines.
9. Will the guitar coils work into a resistive load? the 100nF capacitor you tried has an impedance of 1k6 at 1 khZ. A 1k input resistor might help, but it would be less effective than a cap at higher frequencies.
IDENTIFYING THE NOISE COUPLING PATHS ON YOUR BOARD.
This is how I would test your board to find how noise is getting in.
1. Unplug the pyboard. Program it with your noisy script running in a loop. Unplug the USB cable and run it from a 6V or 9V battery.
2. Jumper any lines that need to be stable at the pyboard socket. For example tie SPI CS high through a 100k resistor to V+ (5V). Even if it's a 3V3 input 100k to 5V won't hurt it.
3. Move the pyboard around close to your board. Is it noisy? If so you have a problem with radiated noise. You need to reduce you input impedance or reduce loop areas. or quieten the pyboard. Try a bigger cap at the supply pins, eg low ESR electro.
4. Connect the pyboard to your PCB ground with one short wire. Is it noisier?
5. Remove the battery and connect V+ to the pyboard. Is it noisy? If so filter the V= with the same inductor and capacitors you use in the SMPS. Did that help?
6. Now connect SPI back. Is it noisy? Try RC filters on the SPI lines.
7. Find out what resistive load the coils can work into without signal loss.
8. Look at your layout. There is a trace blocking C7 from from the power supply side of the GND plane. Its GND path to the power supply is up around the pyboard pins then down the middle of the pyboard where it picks up digital GND noise.
9. Try making a cut in the GND plane between the pyboard and the analog switches. Go right up around the resistors then over to the top edge of the board near U4. link up any bit of analog GND plane that got separated. Jumper C7 GND over the trace to the low side of the GND plane. This gives you a star point at the power supply and digital supply current won't flow in the analog side of the plane.
Its taken a lot of reading and trial and error to understand all this. I hope it helps. Understanding all your noise sources and how they couple is the key. Let me know the results of each test.
Last edited by chrismas9
on Sun Oct 16, 2016 9:33 am, edited 1 time in total.