Here is my board
https://www.st.com/en/evaluation-tools/ ... 767zi.html
It has a STM32F767ZI mcu.
MCU datasheet didn't had much about flash but I found this doc
https://www.st.com/resource/en/applicat ... ronics.pdf
As my F767 has 2MB dual bank, I guess the required sectors are defined on page #18.
As it's dual bank, things getting even less clear to me.
So here is what i have found out so far (please correct me if i am wrong).
Memory table as i understand it (note two sheets for dual and single bank):
https://docs.google.com/spreadsheets/d/ ... sp=sharing
As my MCU has dual bank memory, I think numbers in stm32f767.ld file does not utilize 2 MB.
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FLASH on line #8 has correct starting address 0x08000000 and correct LENGTH of 2048K.
FLASH_ISR uses sector 0 but it should be 16K for dual bank? Looks like 32K is for single bank flash
FLASH_APP uses 1-11 sectors but for dual bank it would be 1008K not 2016K so I guess it's also for single bank.
FLASH_FS uses 1-3 sectors and LENGTH is 96K so it's also for single bank.
FLASH_TEXT uses sectors 4-7 so it's also for single bank.
What happens with sectors 8-11? Are they unused? Why?
Possibly I should adjust ORIGIN and LENGTH to match dual bank, so here are my guesses:
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FLASH - the same
FLASH_ISR - should I use 0-1 sectors to make it 32K? Would it be better to use 0-3 sectors to make it 64K?
FLASH_APP - ORIGIN after FLASH_ISR; LENGTH - to sector 23?
FLASH_FS - ORIGIN same as FLASH_APP; LENGTH?
FLASH_TEXT - ORIGIN after FLASH_FS; LENGTH - till end of FLASH_APP?
There is a note on
https://github.com/micropython/micropyt ... board.h#L1
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// Note: if the board shows odd behaviour check the option bits and make sure nDBANK is
// set to make the 2MByte space continuous instead of divided into two 1MByte segments.
How to set it?
Next file flashbdev.c has these definitions:
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#elif defined(STM32F746xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx)
// The STM32F746 doesn't really have CCRAM, so we use the 64K DTCM for this.
#define CACHE_MEM_START_ADDR (0x20000000) // DTCM data RAM, 64k
#define FLASH_SECTOR_SIZE_MAX (0x08000) // 32k max
#define FLASH_MEM_SEG1_START_ADDR (0x08008000) // sector 1
#define FLASH_MEM_SEG1_NUM_BLOCKS (192) // sectors 1,2,3: 32k+32k+32=96k
I can't find anywhere cache memory start address.
FLASH_SECTOR_SIZE_MAX is 256K but should be 64K because of cache size?
No ideas about FLASH_MEM_SEG1_NUM_BLOCKS.
In
viewtopic.php?f=3&t=3702&p=22627&p22627#p22612 Drako defines SEG2:
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#define FLASH_MEM_SEG2_START_ADDR (0x08100000) // sector 8
#define FLASH_MEM_SEG2_NUM_BLOCKS (256) // sector 8,9,10,11: 4*32k=128k
What happens next? Is it appended to SEG1?
And the last part in file flash.c:
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static const flash_layout_t flash_layout[] = {
{ 0x08000000, 0x08000, 4 }, // start of bank1? 32K stands sector size? 4 sectors of this size?
{ 0x08020000, 0x20000, 1 }, // 1 sector with 128K
{ 0x08040000, 0x40000, 3 }, // 3 sectors with 256K; why only 3 not 7?
{ 0x08100000, 0x40000, 4 }, // start of bank2; remaining 4 sectors?
};
If my MCU has dual bank, shouldn't here be defined both banks separately?
Sorry for a long post. Any help appreciated.