Porting Mirocpython to Risc V ?
Posted: Thu Oct 22, 2015 9:42 am
We got a small FPGA reserarch project funded. We consider running Micropython on a Risc V core on an FPGA.
Having micropython as an interpreter would make things easy on the higher levels.
We do our own Lattice based FPGA board with Flash and Memory and interfaces, so we are flexible
on that side.
Is someone here interested in porting micropython to the Risc V architecture?
We even would pay some money.
Description of Risc-V and gnu tools you can find at http://riscv.org/
I hope to hear from you.
The ultimate goal of the funded project is an FPGA based IoT gatway with a lot of very flexible interfaces (mostly PMOD modules) taken care
in the FPGA handling. (think micropython board on interface steroids)
Thanx
Having micropython as an interpreter would make things easy on the higher levels.
We do our own Lattice based FPGA board with Flash and Memory and interfaces, so we are flexible
on that side.
Is someone here interested in porting micropython to the Risc V architecture?
We even would pay some money.
Description of Risc-V and gnu tools you can find at http://riscv.org/
I hope to hear from you.
The ultimate goal of the funded project is an FPGA based IoT gatway with a lot of very flexible interfaces (mostly PMOD modules) taken care
in the FPGA handling. (think micropython board on interface steroids)
Thanx