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Re: opposite polarities on the 2 DACs
Posted: Mon Mar 05, 2018 7:09 pm
by chuckbook
Hi Andre, I may have missed it but can you provide us with the content of your buf or content of step_b12.dat ?
Re: opposite polarities on the 2 DACs
Posted: Mon Mar 05, 2018 7:58 pm
by andreo
Re: opposite polarities on the 2 DACs
Posted: Tue Mar 06, 2018 7:33 am
by pythoncoder
Hi Andre,
I'm afraid I'm foxed by this: I can neither replicate it nor identify a possible cause. Perhaps someone else will enlighten us and write a reproducible test case. Then we could fix it or raise an issue. I think it's unlikely to be a defective Pyboard but who knows?
I'll come back if I think of a fresh approach.
Regards, Pete
Re: opposite polarities on the 2 DACs
Posted: Tue Mar 06, 2018 9:50 am
by andreo
Hi Peter,
The mystery is still there...
(I got the same behavior with the DAC.triangle() function.)
It has been a pleasure to have your help and it definitively raised my interest in the pyboard.
I'll keep this one with my collectibles, with my old Apple II, a 1983 IBM PC, a prototype 8087...
As I'll explore more technical aspects of the pyboard, be sure we'll meet in another thread of the forum.
Best regards,
Andre
Re: opposite polarities on the 2 DACs
Posted: Tue Mar 06, 2018 6:36 pm
by andreo
Hi Peter,
Some news:
just
reading the DAC registers with stm.mem32 changed the results !!!
the files are in
https://www.proximuscloud.be/web/app/sh ... pijdmt6mbj
The 2 signals are (almost) as expected, but DAC 2 seems to use the analog buffer and has a reduced voltage.
Only explanation is that I have a pyboard with a
Qubit.
Somebody replaced a good old normal 0/1 bit with a Qubit that can change value when reading it.
(beware theoretical physicists !)
Andre
Re: opposite polarities on the 2 DACs
Posted: Wed Mar 07, 2018 9:50 am
by chuckbook
This looks like a broken output buffer op-amp. The write_timed driver enables the output driver (inverting/scaling) per default.
This is ok for most use cases but using the output amp reduces max. conversion rate and the output has to be calibrated in order to achieve full precision. Of course it is possible to damage the output stage.
I don't know if it is possible to switch off output buffering with the default firmware. If it can be done it would be worth giving it try.
However, if precision is required I would always turn of internal buffering and use external components to reduce output impedance.
Unfortunately you may have to cancel your ticket to Stockholm as it is definitely not a Q-Bit
Re: opposite polarities on the 2 DACs
Posted: Wed Mar 07, 2018 11:04 am
by andreo
Hi Peter and chuckbook,
I turned output buffering off with
Code: Select all
DAC_CR = 0x40007400
BOFF2 = 0x00020000
stm.mem32[DAC_CR] = stm.mem32[DAC_CR] | BOFF2
and
it worked.
See RM0090 Reference manual
www.st.com/resource/en/reference_manual/dm00031020.pdf
Digital-to-analog converter (DAC) chapter 14 page 433
Bit 17 BOFF2: DAC channel2 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
Andre
Re: opposite polarities on the 2 DACs
Posted: Thu Mar 08, 2018 6:14 am
by pythoncoder
Hi Andre,
I'm aware of the output buffer. It is non-inverting. The main effect of using it is to restrict the maximum positive and negative excursion of the output, so with the buffer present the output typically lies in the range 0.2V to Vdd-0.2V. As @chuckbook says, an external buffer is best if you want low impedance and accuracy.
So I'm still foxed by the results you're getting. You could have a rare example of a defective board, but as a hardware fault an intermittent voltage inversion is a very odd failure mechanism.
Regards, Pete
Re: opposite polarities on the 2 DACs
Posted: Thu Mar 08, 2018 9:06 am
by chuckbook
Most likely the buffer op-amp of the port is damaged. This would explain the symptoms.
According to the sparse documentation of chip internals the output op-amp is indeed inverting and the DAC output is also (digital) inverted
if buffer mode is selected. So if the op-amp is broken an inverted (and probably reduced) voltage would be seen on the output pin.
Disabling buffered mode will isolate the op-amp and give correct (but high impedance) results.
Re: opposite polarities on the 2 DACs
Posted: Thu Mar 08, 2018 3:01 pm
by andreo
Hi Peter and chuckbook,
chuckbook wrote
Most likely the buffer op-amp of the port is damaged. This would explain the symptoms.
On top of that, my pyboard doesn't behave the same way as when I signalled the problem and is somewhat erratic.
After resetting the board and restarting, it seems DAC 2 is going thru the buffer.
DAC 1 is never using the buffer.
After setting the BOFF2 bit I get the correct signals: both the same.
DAC 2 with buffer is random, on one of the tests, inversion is clear.
Code: Select all
dac1.write_timed(buf, tim_dac, mode=DAC.CIRCULAR)
dac2.write_timed(buf, tim_dac, mode=DAC.CIRCULAR)
DAC_CR = 0x40007400
BOFF1 = 0x00000002
BOFF2 = 0x00020000
for n in range(10):
utime.sleep_ms(2000)
stm.mem32[DAC_CR] = stm.mem32[DAC_CR] | BOFF1
stm.mem32[DAC_CR] = stm.mem32[DAC_CR] | BOFF2
utime.sleep_ms(2000)
stm.mem32[DAC_CR] = stm.mem32[DAC_CR] & (BOFF1 ^ 0xffffffff)
stm.mem32[DAC_CR] = stm.mem32[DAC_CR] & (BOFF2 ^ 0xffffffff)
Thanks to the faulty board and to both of you I learned quite a few things...
Looking forward to learn some ARM assembler on the pyboard too.
(don't worry for my mental health, I have written a lot of KLOCs of IBM/360, 6502, 8086, HP 2114B assembler in the past, it couldn't get worse)
Andre