Controlling Slew Rate of GPIO

[chuckbook]

BTW, it is interesting that Rds seems to be constant. So I guess it is just a variation of the gate area or using multiple gates.

[pythoncoder]

I must admit I can't figure out how it works. But it evidently does I wonder if capacitance is somehow added to the pin to reduce the slew rate? Or might the "slow" MOSFETs use the Miller effect to reduce the slew rate while retaining a low Rdson?

[chuckbook]

If I remember correctly the (usually unwanted) parasitic capacity from overlapping gate and drain is indeed called Miller capacity.

[pythoncoder]

Miller capacitance is that between gate and drain, or base and collector in a bipolar transistor. Not to mention anode and grid in a thermionic valve

The key point about it is that if there's a resistance between the signal source and the control electrode, the effect of negative feedback causes the rate of change (or bandwidth) on the output to be limited; the feedback causes a small capacitance to have an unduly large effect. Usually this is undesirable but it struck me that in this case it might be used for slew rate limiting. In integrated circuits capacitors are expensive but a deliberately "bad" device geometry and the Miller effect could limit slew rate without limiting the current drive capability.