RCC_CSR and resets

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Gordon_Hardman
Posts: 68
Joined: Sat May 03, 2014 11:31 pm

RCC_CSR and resets

Post by Gordon_Hardman » Tue Jul 14, 2015 10:21 pm

I am trying to tell what caused the Pyboard to reset- pin reset, brownout, watchdog etc. Apparently the upper bits in the RCC_CSR register are used for this. I have been trying to find a good reference on the micropython stm module, but only find bits and pieces. I discovered from the STM manual that CSR is at an offset of 0x74. It doesn't say, but I am guessing it is from stm.RCC. So I tried:

Code: Select all

>>> import stm                                                                  
>>> print(bin(stm.mem32[stm.RCC + 0x74]))                                       
0b1110000000000000000000000000                                                  
>>>                                                                             
>>>  
This looks sort of plausible, I will play with it some more, but can anyone confirm I am accessing the right register?

Gordon_Hardman
Posts: 68
Joined: Sat May 03, 2014 11:31 pm

Re: RCC_CSR and resets

Post by Gordon_Hardman » Wed Jul 15, 2015 3:12 pm

I added the following code to my "main.py". It follows what is on P200/201 of STM's RM0090 reference manual.

Code: Select all

RCC_CSR = stm.mem32[stm.RCC + 0x74]  #reset info in high bits in this register
RST_flags = {'BORRS_TF' : (RCC_CSR >> 25) & 1,
            'PIN_RSTF'  : (RCC_CSR >> 26) & 1,
            'POR_RSTF'  : (RCC_CSR >> 27) & 1,
            'SFT_RSTF'  : (RCC_CSR >> 28) & 1,
            'IWDG_RSTF' : (RCC_CSR >> 29) & 1,
            'WWDG_RSTF' : (RCC_CSR >> 30) & 1,
            'LPWR_RSTF' : (RCC_CSR >> 31) & 1}
print('Reset flags: ', RST_flags)
stm.mem32[stm.RCC + 0x74] 1 << 24 # now clear the flags, so they will not persist

Gordon_Hardman
Posts: 68
Joined: Sat May 03, 2014 11:31 pm

Re: RCC_CSR and resets

Post by Gordon_Hardman » Wed Jul 15, 2015 5:40 pm

There was a minor typo in the above. I extended it, to print out one case. Just like with PICs, there is a logic tree that must be followed to uniquely determine the cause.

Code: Select all

RCC_CSR = stm.mem32[stm.RCC + 0x74]  #reset info in high bits in this register
RST_flags = {'BORR_RSTF' : (RCC_CSR >> 25) & 1,
            'PIN_RSTF'  : (RCC_CSR >> 26) & 1,
            'POR_RSTF'  : (RCC_CSR >> 27) & 1,
            'SFT_RSTF'  : (RCC_CSR >> 28) & 1,
            'IWDG_RSTF' : (RCC_CSR >> 29) & 1,
            'WWDG_RSTF' : (RCC_CSR >> 30) & 1,
            'LPWR_RSTF' : (RCC_CSR >> 31) & 1}
print('Reset flags: ', RST_flags)
stm.mem32[stm.RCC + 0x74] = (1 << 24) # now clear the flags, so they will not persist

if ((RST_flags['PIN_RSTF']  == 1) and 
    (RST_flags['BORR_RSTF'] == 1) and
    (RST_flags['POR_RSTF']  == 1) and
    (RST_flags['SFT_RSTF']  == 0) and
    (RST_flags['IWDG_RSTF'] == 0) and
    (RST_flags['WWDG_RSTF'] == 0) and
    (RST_flags['LPWR_RSTF'] == 0)):
    print('Power On Reset')
pyb.delay(2000)

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