Custom port A9G module: help wanted

C programming, build, interpreter/VM.
Target audience: MicroPython Developers.
pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Sat May 25, 2019 6:21 pm

Can you give an example of the code that would cause a root pointer to stuck in the registers? I tried the following one with no success: ptr remains inside the memory.

Code: Select all

void gc_stress_test(void) {
    volatile int delta = 0;
    void* ptr;
    
    // Some significant allocation
    ptr = gc_alloc(400000, 0);
    
    // Make ptr stick around ...
    mp_warning("test", "ptr 0x%p", ptr);
    ptr += delta;
    
    // ... and immidiately call gc_collect ...
    gc_collect();
    
    // ... while preventing ptr to be optimized out
    mp_warning("test", "ptr 0x%p", ptr);
    // gc_dump_info always shows 400000 to be occupied
    gc_dump_info();
}

jickster
Posts: 629
Joined: Thu Sep 07, 2017 8:57 pm

Re: Custom port A9G module: help wanted

Post by jickster » Sat May 25, 2019 6:49 pm

That’s a difficult thing to replicate because it totally depends on how your compiler generates the binary code aka assembly.

I’m not surprised that you’re having a hard time creating that condition because in most(all?) cases, the registers will be flushed to memory.

But I wouldn’t rely on this otherwise one Day you’ll get a weird bug.

Are you having trouble writing code to root-sweep the registers?


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pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Sat May 25, 2019 7:37 pm

Exactly. I have a code which compiles and runs but since this is my first asm code I have no idea whether it will actually work in the wild.

https://github.com/pulkin/micropython/b ... gchelper.s

pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Sun May 26, 2019 6:45 pm

I saw two kinds of SSL/TLS bundled with mp: which one should I compile in?

pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Sun Jun 09, 2019 10:14 pm

I need help adding SSL to my module.

pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Mon Nov 04, 2019 10:48 am

I am happy to announce that [the port](https://github.com/pulkin/micropython/b ... /README.md) is advancing. In terms of hardware, a number of things are working reliably including GPIO, GPRS network, SMS, file IO, system and power things. Now I am looking at `micropython.native/viper` and how it is implemented. I found that several architectures are hard-coded in `mp`: for example, files `py/emitinlinextensa.c` and `py/emitinlinethumb.c`. Is there a minimal chance of having RISC XCPU (whatever that means) in-line compiler for micropython?

FIY, toolchain asm compiler options:
```
mips-elf-as --warn -EL -march=xcpu -mtune=xcpu -o build/gchelper.o gchelper.s
```

User avatar
jimmo
Posts: 869
Joined: Tue Aug 08, 2017 1:57 am
Location: Sydney, Australia

Re: Custom port A9G module: help wanted

Post by jimmo » Mon Nov 04, 2019 11:10 am

It's quite a lot of work, but yes asm*.c and emit*.c are what you would need to duplicate for your architecture.

How important is supporting native/viper for your board? Have you run into performance bottlenecks?

pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Mon Nov 04, 2019 11:18 am

It is just something that I was considering implementing. I won't for now then.

pulkin
Posts: 25
Joined: Tue Feb 19, 2019 10:22 pm

Re: Custom port A9G module: help wanted

Post by pulkin » Sun Nov 10, 2019 6:07 pm

I have a display over SPI now. It is quite slow. The main reason, I believe, is python library which drives it pixel-by-pixel.

https://github.com/boochow/MicroPython-ST7735

What is the best way to speed it up?

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